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ISLPED
1995
ACM
100views Hardware» more  ISLPED 1995»
14 years 3 months ago
Simultaneous scheduling and binding for power minimization during microarchitecture synthesis
ABSTRACT { Sub-micron technologies and the increasing size and complexity of integrated components have aggravated the e ect of long interconnects and buses, compared to that of ga...
Aurobindo Dasgupta, Ramesh Karri
ISLPED
1997
ACM
81views Hardware» more  ISLPED 1997»
14 years 3 months ago
A method of redundant clocking detection and power reduction at RT level design
This paper proposes a novel method to estimate and to reduce redundant power of synchronous circuits at RT level design. Because much redundant power is caused by redundant clocki...
Mitsuhisa Ohnishi, Akihisa Yamada, Hiroaki Noda, T...
DATE
1997
IEEE
124views Hardware» more  DATE 1997»
14 years 3 months ago
A controller testability analysis and enhancement technique
This paper presents a testability analysis and improvement technique for the controller of an RT level design. It detects hard-to-reachstates by analyzing both the data path and t...
Xinli Gu, Erik Larsson, Krzysztof Kuchcinski, Zebo...