ABSTRACT { Sub-micron technologies and the increasing size and complexity of integrated components have aggravated the eect of long interconnects and buses, compared to that of ga...
This paper proposes a novel method to estimate and to reduce redundant power of synchronous circuits at RT level design. Because much redundant power is caused by redundant clocki...
This paper presents a testability analysis and improvement technique for the controller of an RT level design. It detects hard-to-reachstates by analyzing both the data path and t...
Xinli Gu, Erik Larsson, Krzysztof Kuchcinski, Zebo...