Methodologies and Algorithms for Testing Switch-Based NoC Interconnects

In this paper, we present two novel methodologies for testing the interconnect fabrics of network-on-chip (NoC) based chips. Both use the concept of recursive testing, with different degrees of parallelism in each case. Our test methodologies cover the logic switching blocks and the FIFO buffers that are the basic components of NoC fabrics. The paper concludes with test time evaluations for different NoC topologies and sizes.

• Type: Conference
• Year: 2005
• Where: DFT
• Authors: Cristian Grecu, Partha Pratim Pande, Baosheng Wang, André Ivanov, Res Saleh
• Keywords: DFT 2005, Hardware, Logic Switching Blocks, NoC Fabrics, Test Time Evaluations