Methodologies for Tolerating Cell and Interconnect Faults in FPGAs

—The very high levels of integration and submicron device sizes used in current and emerging VLSI technologies for FPGAs lead to higher occurrences of defects and operational faults. Thus, there is a critical need for fault tolerance and reconfiguration techniques for FPGAs to increase chip yields (with factory reconfiguration) and/or system reliability (with field reconfiguration). We first propose techniques utilizing the principle of node-covering to tolerate logic or cell faults in SRAM-based FPGAs. A routing discipline is developed that allows each cell to cover—to be able to replace—its neighbor in a row. Techniques are also proposed for tolerating wiring faults by means of replacement with spare portions. The replaceable portions can be individual segments, or else sets of segments, called “grids.” Fault detection in the FPGAs is accomplished by separate testing, either at the factory or by the user. If reconfiguration around faulty cells and wiring is performed at the...

• Type: Journal
• Year: 1998
• Where: TC
• Authors: Fran Hanchek, Shantanu Dutt
• Keywords: Chip Yield, Fault Tolerance, FPGA, Information Technology, TC 1998