—This paper suggests a technique for analyzing the performance of checkpointing schemes with task duplication. We show how this technique can be used to derive the average execut...
—Many modern Field Programmable Logic Arrays (FPGAs) use lookup table (LUT) logic blocks which can be programmed to realize any function of a fixed number of inputs. It is possib...
—The architecture of a device that is optimized for wireless information access and display of multimedia data is substantially different than configurations designed for portabl...
Thomas E. Truman, Trevor Pering, Roger Doering, Ro...
—High instruction cache hit rates are key to high performance. One known technique to improve the hit rate of caches is to minimize cache interference by improving the layout of ...
—Authentication using a path of trusted intermediaries, each able to authenticate the next in the path, is a well-known technique for authenticating channels in a large distribut...
—This paper describes the methods used to formulate and validate the memory subsystem of the cache-coherent Sun Scalable emory MultiProcessor (S3.mp) at three levels of abstracti...
Fong Pong, Michael C. Browne, Gunes Aybay, Andreas...
In [1], Duprat and Muller introduced the ingenious “Branching CORDIC” algorithm. It enables a fast implementation of CORDIC algorithm using signed digits and requires a consta...
ion Techniques for Validation Coverage Analysis and Test Generation Dinos Moundanos, Jacob A. Abraham, Fellow, IEEE, and Yatin V. Hoskote —The enormous state spaces which must be...
Dinos Moundanos, Jacob A. Abraham, Yatin Vasant Ho...