Microcaches

We describe a radically new cache architecture and demonstrate that it offers a huge reduction in cache cost, size and power consumption whilst maintaining performance on a wide range of programs. We achieve this by giving the compiler control of the cache and by allowing regions of the cache to be allocated to specific program objects. Our approach has widespread application, especially in media processing and scientific computing. 1 Microprocessor Caches Current computer architectures rely heavily on the use of cache memory to enable the processor to operate at high speed. Cache management hardware takes no account of the characteristics of specific programs, and in many simple cases performs very inefficiently. An obvious example of this is in the copying program for i=0 to 500 a i = b i ; Here a large region of the cache will be taken over by data which is used only once and may interfere with other objects (instruction blocks or data) competing for the same space. We propose t...

• Type: Conference
• Year: 1999
• Where: HIPC
• Authors: David May, Dan Page, James Irwin, Henk L. Muller
• Keywords: Cache, Cache Cost, Cache Management Hardware, Distributed And Parallel Computing, HIPC 1999