Minimizing resources in a repeating schedule for a split-node data-flow graph

Many computation-intensive or recursive applications commonly found in digital signal processing and image processing applications can be represented by data-flow graphs (DFGs). In our previous work, we proposed a new technique, extended retiming, which can be combined with minimal unfolding to transform a DFG into one which is rate-optimal. The result, however, is a DFG with split nodes, a concise representation for pipelined schedules. This model and the extraction of the pipelined schedule it represents have heretofore not been explored. In this paper, we demonstrate one scheduling algorithm for such graphs, and then discuss a way to reduce the hardware requirements of the resulting schedule. In the process, we state and prove a tight upper bound on the minimum number of processors required to execute the static schedule produced by our algorithms. Finally, we demonstrate our methods on a specific example. Categories and Subject Descriptors J.6 [Computer-Aided Engineering]: Compu...

• Type: Conference
• Year: 2002
• Where: GLVLSI
• Authors: Timothy W. O'Neil, Edwin Hsing-Mean Sha
• Keywords: Digital Signal Processing, GLVLSI 2002, Image Processing Applications, Tight Upper Bound, VLSI