MISC: a Multiple Instruction Stream Computer

This paper describes a single chip Multiple Instruction Stream Computer (MISC) capable of extracting instruction level parallelism from a broad spectrum of programs. The MISC architecture uses multiple asynchronous processing elements to separate a program into streams that can be executed in parallel, and integrates a conflict-free message passing system into the lowest level of the processor design to facilitate low latency intra-MISC communication. This approach allows for increased machine parallelism with minimal code expansion, and provides an alternative approach to single instruction stream multi-issue machines such as SuperScalar and VLIW. - 1 

• Type: Conference
• Year: 1992
• Where: MICRO
• Authors: Gary S. Tyson, Matthew K. Farrens, Andrew R. Pleszkun
• Keywords: Hardware, Instruction Level Parallelism, Instruction Stream, MICRO 1992, Multiple Instruction Stream