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MICRO
1992
IEEE
128views Hardware» more  MICRO 1992»
14 years 3 months ago
MISC: a Multiple Instruction Stream Computer
This paper describes a single chip Multiple Instruction Stream Computer (MISC) capable of extracting instruction level parallelism from a broad spectrum of programs. The MISC arch...
Gary S. Tyson, Matthew K. Farrens, Andrew R. Plesz...
MICRO
1992
IEEE
133views Hardware» more  MICRO 1992»
14 years 3 months ago
Code generation schema for modulo scheduled loops
Software pipelining is an important instruction scheduling technique for efficiently overlapping successive iterations of loops and executing them in parallel. Modulo scheduling i...
B. Ramakrishna Rau, Michael S. Schlansker, Parthas...
MICRO
1992
IEEE
124views Hardware» more  MICRO 1992»
14 years 3 months ago
A shape matching approach for scheduling fine-grained parallelism
- We present a compilation technique for scheduling parallelism on fine grained asynchronous MIMD systems. The shape scheduling algorithm is introduced that utilizes the flexibilit...
Brian A. Malloy, Rajiv Gupta, Mary Lou Soffa
MICRO
1992
IEEE
99views Hardware» more  MICRO 1992»
14 years 3 months ago
An investigation of the performance of various dynamic scheduling techniques
An important design decision in the implementation of a superscalar processor is the amount of hardware to allocate to the instruction scheduling mechanism. Dynamic scheduling pro...
Michael Butler, Yale N. Patt