Misleading energy and performance claims in sub/near threshold digital systems

Abstract-- Many of us in the field of ultra-low-Vdd processors experience difficulty in assessing the sub/near threshold circuit techniques proposed by earlier papers. This paper investigates five major pitfalls which are often not appreciated by researchers when claiming that their circuits outperform others by working at a lower Vdd with a higher energy-efficiency. These pitfalls include: i) overlook the impacts of different technologies and different Vth definitions, ii) only emphasize energy reduction but ignore severe throughput degradation, or expect impractical pipelining depth and parallelism degree to compensate this throughput degradation, iii) unrealistically assume that memory's Vdd and energy could scale as well as standard cells, iv) use the highest temperature as the worst timing corner as in the super-threshold, but in fact negative temperature becomes much more detrimental in the sub/near threshold regime, v) pursue just-in-need Vdd to compensate effects of PVT, b...

• Type: Journal
• Year: 2010
• Where: ICCAD
• Authors: Yu Pu, Xin Zhang, Jim Huang, Atsushi Muramatsu, Masahiro Nomura, Koji Hirairi, Hidehiro Takata, Taro Sakurabayashi, Shinji Miyano, Makoto Takamiya, Takayasu Sakurai
• Keywords: Fact Negative Temperature, Hardware, ICCAD 2010, Severe Throughput Degradation, Threshold Circuit Techniques