A mixed-clock issue queue design for globally asynchronous, locally synchronous processor cores

Ever shrinking device sizes and innovative micro-architectural and circuit design techniques have made it possible to have multi-million transistor systems running at multi-gigahertz speeds. However, such a tremendous computational capability comes at a high price in terms of power consumption and design effort in distributing a global clock signal across the chip. One of the most promising strategies that addresses these issues is the Globally Asynchronous, Locally Synchronous (GALS) design style where multiple domains are governed by different, locally generated clocks. Due to its inherent complexity, a possible driver application for such a design style is the case of superscalar, out-of-order processors. While micro-architectural evaluations for GALS microprocessors have been made available recently, no concrete implementations have been analyzed in a detailed way. In this paper we propose a mixed-clock issue queue design for high-end, out-of-order superscalar processors, able t...

• Type: Conference
• Year: 2003
• Where: ISLPED
• Authors: Venkata Syam P. Rapaka, Diana Marculescu
• Keywords: Design Style, ISLPED 2003, Issue Queue Design, Issue Queues