Modeling and verification of high-speed wired links with Verilog-AMS

—Behavioral modeling with virtual built-in self-test verification of high-speed wired link designs is described in this paper. Our procedure is based on principles of top-down mixed-signal design combined with a behavioral description language and mixed-mode simulations. The use of VerilogAMS is applied not only to circuit modeling but also for representing noise on the input signal. This approach provides system-level jitter tolerance estimation, circuit critical path search and overall design verification. Coding examples and simulation results are included.

• Type: Conference
• Year: 2006
• Where: ISCAS
• Authors: Ming-Ta Hsieh, Gerald E. Sobelman
• Keywords: Built-in Self-test Verification, ISCAS 2006, System-level Jitter Tolerance, Top-down Mixed-signal Design