Module Graph Merging and Placement to Reduce Reconfiguration Overheads in Paged FPGA Devices

Reconfiguration time in dynamically-reconfigurable modular systems can severely limit application run-time compared to the critical path delay. In this paper we present a novel method to reduce reconfiguration time by maximising wire use and minimising wire reconfiguration. This builds upon our previously-presented methodology for creating modular, dynamically-reconfigurable applications targeted to an FPGA. The application of our techniques is demonstrated on an optical flow problem and show that graph merging can reduce reconfiguration delay by 50%.

• Type: Conference
• Year: 2007
• Where: FPL
• Authors: Shannon Koh, Oliver Diessel
• Keywords: Critical Path Delay, Dynamically-reconfigurable Modular Systems, FPL 2007, Hardware, Reconfiguration Time