FPL 2007 - PDF Preprint Papers

FPL 2007 International Conference on Field Programmable Logic and Applications

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FPL
2007
Springer

198views Hardware» more FPL 2007»

Floating-Point Trigonometric Functions for FPGAs

14 years 6 months ago

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Field-programmable circuits now have a capacity that allows them to accelerate ﬂoating-point computing, but are still missing core libraries for it. In particular, there is a ne...

Jérémie Detrey, Florent de Dinechin

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Id	Views	Title	Status

1	198	Floating-Point Trigonometric Functions for FPGAs	claim
2	190	The ANDRES Project: Analysis and Design of Run-Time Reconfigurable, Heterogeneous Systems	claim
3	190	Automatic Accuracy-Guaranteed Bit-Width Optimization for Fixed and Floating-Point Systems	claim
4	178	Exploring Alternative 3D FPGA Architectures: Design Methodology and CAD Tool Support	claim
5	176	ReconOS: An RTOS supporting Hard- and Software Threads	claim
6	171	A Banded Smith-Waterman FPGA Accelerator for Mercury BLASTP	claim
7	154	Physical Unclonable Functions, FPGAs and Public-Key Crypto for IP Protection	claim
8	150	Discrete Event Simulation of Molecular Dynamics with Configurable Logic	claim
9	146	Efficient External Memory Interface for Multi-processor Platforms Realized on FPGA Chips	claim
10	142	DWARV: DelftWorkBench Automated Reconfigurable VHDL Generator	claim
11	141	Analysis of Kernel Effects on Optimisation Mismatch in Cache Reconfiguration	claim
12	140	An area-efficient alternative to adaptive median filtering in FPGAs	claim
13	138	Bringing High-Performance Reconfigurable Computing to Exact Computations	claim
14	137	Multi-processor System-level Synthesis for Multiple Applications on Platform FPGA	claim
15	136	A Load/Store Unit for a Memcpy Hardware Accelerator	claim
16	133	Efficient Modeling and Floorplanning of Embedded-FPGA Fabric	claim
17	128	Embedded Programmable Logic Core Enhancements for System Bus Interfaces	claim
18	127	Domain-Specific Hybrid FPGA: Architecture and Floating Point Applications	claim
19	126	A Time-Triggered Network-on-Chip	claim
20	126	A Behavioral Synthesis Approach for Distributed Memory FPGA Architectures	claim
21	125	Run-time Partial Reconfiguration for Removal, Placement and Routing on the Virtex-II-Pro	claim
22	124	HARTES Toolchain Early Evaluation: Profiling, Compilation and HDL Generation	claim
23	124	A Quantitative Prediction Model for Hardware/Software Partitioning	claim
24	122	Efficient FPGA-based multipliers for F_3^97 and F_3^(6*97)	claim
25	121	Comrade - A Compiler for Adaptive Computing Systems Using a Novel Fast Speculation Technique	claim
26	121	Improving Pipelined Soft Processors with Multithreading	claim
27	120	Design Methodology and Trade-offs Analysis for Parameterized Dynamically Reconfigurable Processor Arrays	claim
28	116	Adventures with a Reconfigurable Research Platform	claim
29	115	Hardware/Software Process Migration and RTL Simulation	claim
30	111	Adaptive Thermoregulation for Applications on Reconfigurable Devices	claim
31	109	Hybridthreads Compiler: Generation of Application Specific Hardware Thread Cores from C	claim
32	107	L4: An FPGA-Based Accelerator for Detailed Maze Routing	claim
33	106	RAMP Blue: A Message-Passing Manycore System in FPGAs	claim
34	106	Monte Carlo Logarithmic Number System for Model Predictive Control	claim
35	105	An Execution Model for Hardware/Software Compilation and its System-Level Realization	claim
36	105	A floating-point Extended Kalman Filter implementation for autonomous mobile robots	claim
37	105	Time Predictable CPU and DMA Shared Memory Access	claim
38	101	Formal Modeling of Process Migration	claim
39	100	Clock-Aware Placement for FPGAs	claim
40	99	Disjoint Pattern Enumeration for Custom Instructions Identification	claim
41	98	Module Graph Merging and Placement to Reduce Reconfiguration Overheads in Paged FPGA Devices	claim
42	97	An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems	claim
43	96	Implementation of a 2-D 8x8 IDCT on the Reconfigurable Montium Core	claim
44	94	A Many-core Implementation based on the Reconfigurable Mesh Model	claim
45	94	An OCM based shared Memory controller for Virtex 4	claim
46	89	Evolutionary Search Applied to Reconfigurable Analogue Control	claim
47	80	A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems	claim
48	80	Wires On Demand: Run-Time Communication Synthesis for Reconfigurable Computing	claim
49	78	Dynamic Cache Switching in Reconfigurable Embedded Systems	claim

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