Module selection and data format conversion for cost-optimal DSP synthesis

In high level synthesis each node of a synchronous dataflow graph (DFG) is scheduled to a specific time and allocated to a processor. In this paper we present new integer linear programming (ILP) models which generate a blocked schedule for a DFG with implicit retiming, pipelining, and unfolding while performing module selection and data format conversion. A blocked schedule is a schedule which overlaps multiple iterations of the DFG to guarantee a minimum number of processors. Component modules are selected from a library of processors to minimize cost. Furthermore, we include data format converters between processors of different data formats. In addition, we minimize the unfolding factor of the blocked schedule.

• Type: Conference
• Year: 1994
• Where: ICCAD
• Authors: Kazuhito Ito, Lori E. Lucke, Keshab K. Parhi
• Keywords: Blocked Schedule, Data Formats, Hardware, ICCAD 1994, Synchronous Dataflow Graph