ICCAD 1994 - PDF Preprint Papers

ICCAD 1994 International Conference on Computer-Aided Design

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ICCAD
1994
IEEE

200views Hardware» more ICCAD 1994»

Techniques for crosstalk avoidance in the physical design of high-performance digital systems

14 years 4 months ago

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Interconnectperformance does not scale well into deep submicron dimensions, and the rising number of analog effects erodes tal abstraction necessary for high levels of integration...

Desmond Kirkpatrick, Alberto L. Sangiovanni-Vincen...

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Id	Views	Title	Status

1	200	Techniques for crosstalk avoidance in the physical design of high-performance digital systems	claim
2	151	Multi-way VLSI circuit partitioning based on dual net representation	claim
3	144	Power analysis of embedded software: a first step towards software power minimization	claim
4	139	Switching activity analysis considering spatiotemporal correlations	claim
5	137	Dynamic scheduling and synchronization synthesis of concurrent digital systems under system-level constraints	claim
6	134	Boolean constrained encoding: a new formulation and a case study	claim
7	131	Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs	claim
8	127	Synthesis of concurrent system interface modules with automatic protocol conversion generation	claim
9	125	RISA: accurate and efficient placement routability modeling	claim
10	122	An enhanced flow model for constraint handling in hierarchical multi-view design environments	claim
11	121	A cell-based power estimation in CMOS combinational circuits	claim
12	119	Multi-level network optimization for low power	claim
13	119	Adaptive cut line selection in min-cut placement for large scale sea-of-gates arrays	claim
14	117	Optimization of critical paths in circuits with level-sensitive latches	claim
15	117	Optimal latch mapping and retiming within a tree	claim
16	116	Design of heterogeneous ICs for mobile and personal communication systems	claim
17	115	Fast transient power and noise estimation for VLSI circuits	claim
18	114	Performance-driven synthesis of asynchronous controllers	claim
19	112	Selecting partial scan flip-flops for circuit partitioning	claim
20	111	On modeling top-down VLSI design	claim
21	110	Test pattern generation based on arithmetic operations	claim
22	109	Efficient breadth-first manipulation of binary decision diagrams	claim
23	109	Unified complete MOSFET model for analysis of digital and analog circuits	claim
24	106	On the NP-completeness of regular 2-D FPGA routing architectures and a novel solution	claim
25	105	Register assignment through resource classification for ASIP microcode generation	claim
26	104	Module selection and data format conversion for cost-optimal DSP synthesis	claim
27	102	Clock period constrained minimal buffer insertion in clock trees	claim
28	101	A general framework for vertex orderings, with applications to netlist clustering	claim
29	99	Condition graphs for high-quality behavioral synthesis	claim
30	97	Improving over-the-cell channel routing in standard cell design	claim
31	95	Provably correct high-level timing analysis without path sensitization	claim
32	92	Reuse of design objects in CAD frameworks	claim
33	92	Synthesis of manufacturable analog circuits	claim
34	91	A loosely coupled parallel algorithm for standard cell placement	claim
35	90	Low-cost single-layer clock trees with exact zero Elmore delay skew	claim
36	90	Algorithm selection: a quantitative computation-intensive optimization approach	claim
37	87	On testing delay faults in macro-based combinational circuits	claim
38	83	A new built-in self-test approach for digital-to-analog and analog-to-digital converters	claim
39	82	A new efficient approach to statistical delay modeling of CMOS digital combinational circuits	claim
40	82	Generating instruction sets and microarchitectures from applications	claim
41	82	A timing analysis algorithm for circuits with level-sensitive latches	claim
42	80	Efficient small-signal circuit analysis and sensitivity computations with the PVL algorithm	claim
43	80	Macromodeling of analog circuits for hierarchical circuit design	claim
44	80	Folding a stack of equal width components	claim
45	77	A specified delay accomplishing clock router using multiple layers	claim
46	76	Simultaneous functional-unit binding and floorplanning	claim
47	76	An efficient procedure for the synthesis of fast self-testable controller structures	claim
48	76	Integrating program transformations in the memory-based synthesis of image and video algorithms	claim
49	76	Decomposition methods for library binding of speed-independent asynchronous designs	claim
50	74	Dataflow-driven memory allocation for multi-dimensional signal processing systems	claim
51	74	Perturb and simplify: multi-level boolean network optimizer	claim
52	74	Non-scan design-for-testability of RT-level data paths	claim
53	74	A new approach for factorizing FSM's	claim
54	74	Retiming with non-zero clock skew, variable register, and interconnect delay	claim
55	73	Low power state assignment targeting two-and multi-level logic implementations	claim
56	72	Efficient network flow based min-cut balanced partitioning	claim
57	70	Iterative algorithms for formal verification of embedded real-time systems	claim
58	67	The reproducing placement problem with applications	claim
59	65	Incremental formal design verification	claim
60	61	Simultaneous driver and wire sizing for performance and power optimization	claim
61	59	Fault dictionary compaction by output sequence removal	claim
62	57	Definition and solution of the memory packing problem for field-programmable systems	claim

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