Multiclass Flow Line Models of Semiconductor Manufacturing Equipment for Fab-Level Simulation

—For multiclass flow line models, we identify a class of service times that allow a decomposition of the system into subsets of servers called channels. In each channel, the customer delay is well structured and we develop a recursion to calculate it. The recursions provide an alternative to the elementary evolution equations. By considering batch arrivals and restricting the structure of the model, the recursions can require nearly one order of magnitude less computation than is otherwise possible. Flow lines can be used as models for semiconductor manufacturing equipment such as multicluster or clustered photolithography tools. The models allow for internal wafer buffers and setups that are wafer location dependent. The models have shown to be very accurate in tests with data from clustered photolithography tools in production. As such, the models may serve as good candidates to improve the fidelity of existing equipment models in fablevel simulation. Note to Practitioners—Clus...

• Type: Journal
• Year: 2011
• Where: TASE
• Authors: James R. Morrison
• Keywords: Internal Wafer Buffers, Software Engineering, TASE 2011, Wafer, Wafer Location