Multilevel Hypergraph Partitioning: Application in VLSI Domain

In this paper, we present a new hypergraph partitioning algorithm that is based on the multilevel paradigm. In the multilevel paradigm, a sequence of successively coarser hypergraphs is constructed. A bisection of the smallest hypergraph is computed and it is used to obtain a bisection of the original hypergraph by successively projecting and refining the bisection to the next level finer hypergraph. We evaluate the performance both in terms of the size of the hyperedge cut on the bisection as well as run time on a number of VLSI circuits. Our experiments show that our multilevel hypergraph partitioning algorithm produces high quality partitioning in relatively small amount of time. The quality of the partitionings produced by our scheme are on the average 4% to 23% better than those produced by other state-of-the-art schemes. Furthermore, our partitioning algorithm is significantly faster, often requiring 4 to 15 times less time than that required by the other schemes. Our multile...

• Type: Conference
• Year: 1997
• Where: DAC
• Authors: George Karypis, Rajat Aggarwal, Vipin Kumar, Shashi Shekhar
• Keywords: Computer Architecture, DAC 1997, Hypergraph Partitioning Algorithm, Multilevel Hypergraph, Multilevel Paradigm