Multilevel routing with antenna avoidance

As technology advances into nanometer territory, the antenna problem has caused significant impact on routing tools. The antenna effect is a phenomenon of plasmainduced gate oxide degradation caused by charge accumulation on conductors. It directly influences reliability, manufacturability and yield of VLSI circuits, especially in deep-submicron technology using high density plasma. Furthermore, the continuous increase of the problem size of IC routing is also a great challenge to existing routing algorithms. In this paper, we propose a novel framework for multilevel full-chip routing with antenna avoidance using built-in jumper insertion approach. Compared with the state-of-the-art multilevel routing, the experimental results show that our approach reduced 100% antenna-violated gates and results in fewer wirelength, vias, and delay increase.

• Type: Conference
• Year: 2004
• Where: ISPD
• Authors: Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen
• Keywords: Hardware, ISPD 2004, Multilevel Full-chip Routing, Routing, Routing Algorithms