Multiple Faults: Modeling, Simulation and Test

We give an algorithm to model any given multiple stuck-at fault as a single stuck-at fault. The procedure requires insertion of at most ? ? ? modeling gates, when the multiplicity of the targeted fault is ?. We prove that the modeled circuit is functionally equivalent to the original circuit and the targeted multiple fault is equivalent to the modeled single stuckat fault. The technique allows simulation and test generation for any arbitrary multiple fault in combinational or sequential circuits. We further demonstrate applications to bridgingfault modeling, diagnosis, circuit optimization, and testing of multiply-testable faults. The modeling technique has an additional application in a recently published combinational ATPG method for partial-scan circuits in which some lines are split, leading to a transformation of single stuck-at faults into multiple faults.

• Type: Conference
• Year: 2002
• Where: VLSID
• Authors: Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja
• Keywords: Arbitrary Multiple Fault, Computer Architecture, Multiple Stuck-at Fault, Targeted Multiple Fault, VLSID 2002