VLSID 2002 - PDF Preprint Papers

VLSID 2002 International Conference on VLSI Design

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VLSID
2002
IEEE

207views VLSI» more VLSID 2002»

Synthesis of High Performance Low Power Dynamic CMOS Circuits

15 years 24 days ago

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This paper presents a novel approach for the synthesis of dynamic CMOS circuits using Domino and Nora styles. As these logic styles can implement only non-inverting logic, convent...

Debasis Samanta, Nishant Sinha, Ajit Pal

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Id	Views	Title	Status

1	207	Synthesis of High Performance Low Power Dynamic CMOS Circuits	claim
2	192	Static and Dynamic Variable Voltage Scheduling Algorithms for Real-Time Heterogeneous Distributed Embedded Systems	claim
3	189	Automatic Modeling and Validation of Pipeline Specifications Driven by an Architecture Description Language	claim
4	177	RTL-Datapath Verification using Integer Linear Programming	claim
5	174	Architecture Implementation Using the Machine Description Language LISA	claim
6	172	Improvement of ASIC Design Processes	claim
7	160	PREDICTMOS MOSFET Model and its Application to Submicron CMOS Inverter Delay Analysis	claim
8	160	An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing	claim
9	159	Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon	claim
10	152	Verification of an Industrial CC-NUMA Server	claim
11	151	Mode Selection and Mode-Dependency Modeling for Power-Aware Embedded Systems	claim
12	149	Functional Partitioning for Low Power Distributed Systems of Systems-on-a-Chip	claim
13	149	Development of ASIC Chip-Set for High-End Network Processing Application-A Case Study	claim
14	142	Address Code and Arithmetic Optimizations for Embedded Systems	claim
15	142	Degree-of-Freedom Analysis for Sequential Machines Targeting BIST Quality and Gate Area	claim
16	142	Architecture and Design of a High Performance SRAM for SOC Design	claim
17	138	A Framework for Design Space Exploration of Parameterized VLSI Systems	claim
18	138	ETAM++: Extended Transition Activity Measure for Low Power Address Bus Designs	claim
19	136	Buffered Routing Tree Construction under Buffer Placement Blockages	claim
20	135	An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis	claim
21	132	VLSI Architecture for a Flexible Motion Estimation with Parameters	claim
22	131	Divide-and-Conquer IDDQ Testing for Core-Based System Chips	claim
23	130	Using Randomized Rounding to Satisfy Timing Constraints of Real-Time Preemptive Tasks	claim
24	129	Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis	claim
25	128	System-Level Point-to-Point Communication Synthesis using Floorplanning Information	claim
26	127	Switching Activity Estimation of Large Circuits using Multiple Bayesian Networks	claim
27	127	Design of Asynchronous Controllers with Delay Insensitive Interface	claim
28	126	A Hardware/Software Reconfigurable Architecture for Adaptive Wireless Image Communication	claim
29	125	Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors	claim
30	124	Efficient Approximate Balanced Truncation of General Large-Scale RLC Systems via Krylov Methods	claim
31	123	Compiler-Directed Array Interleaving for Reducing Energy in Multi-Bank Memories	claim
32	122	Evaluating Run-Time Techniques for Leakage Power Reduction	claim
33	122	IEEE 1394a_2000 Physical Layer ASIC	claim
34	120	Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing	claim
35	119	Reducing Library Development Cycle Time through an Optimum Layout Create Flow	claim
36	116	Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization	claim
37	116	Register Transfer Operation Analysis during Data Path Verification	claim
38	116	A Design of Analog C-Matrix Circuits Used for Signal/Data Processing	claim
39	116	Efficient Macromodeling for On-Chip Interconnects	claim
40	115	A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits	claim
41	115	Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLA	claim
42	115	An Adaptive Interconnect-Length Driven Placer	claim
43	114	Embedded DRAM (eDRAM) Power-Energy Estimation for System-on-a-Chip (SoC) Applications	claim
44	114	Minimizing Energy Consumption for High-Performance Processing	claim
45	111	Application of Multi-Domain and Multi-Language Cosimulation to an Optical MEM Switch Design	claim
46	110	Automatic Synthesis of CMOS Operational Amplifiers: A Fuzzy Optimization Approach	claim
47	109	Probabilistic Analysis of Rectilinear Steiner Trees	claim
48	107	Estimation of Maximum Power-Up Current	claim
49	107	Automatic Model Refinement for Fast Architecture Exploration	claim
50	106	SWASAD: An ASIC Design for High Speed DNA Sequence Matching	claim
51	105	A Heuristic for Clock Selection in High-Level Synthesis	claim
52	102	Losses in Multilevel Crossover in VLSI Interconnects	claim
53	100	Layout-Driven Timing Optimization by Generalized De Morgan Transform	claim
54	99	Input Space Adaptive Embedded Software Synthesis	claim
55	98	On Test Scheduling for Core-Based SOCs	claim
56	97	Multiple Faults: Modeling, Simulation and Test	claim
57	97	Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement	claim
58	96	Strategies for Improving Data Locality in Embedded Applications	claim
59	95	A Novel Method to Improve the Test Efficiency of VLSI Tests	claim
60	95	Design of an On-Chip Test Pattern Generator without Prohibited Pattern Set (PPS)	claim
61	95	Consumer Digitization: Accelerating DSP Applications, Growing VLSI Design Challenges	claim
62	94	Timing Yield Calculation Using an Impulse-Train Approach	claim
63	94	A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design	claim
64	92	Electromigration Avoidance in Analog Circuits: Two Methodologies for Current-Driven Routing	claim
65	92	Low Power Solution for Wireless Applications	claim
66	91	Rational ABCD Modeling of High-Speed Interconnects	claim
67	90	Software-Only Bus Encoding Techniques for an Embedded System	claim
68	87	Weight-Based Bus-Invert Coding for Low-Power Applications	claim
69	87	Simultaneous Circuit Transformation and Routing	claim
70	83	Identifying Redundant Wire Replacements for Synthesis and Verification	claim
71	82	Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST	claim
72	81	A New Synthesis of Symmetric Functions	claim
73	79	A Power Minimization Technique for Arithmetic Circuits by Cell Selection	claim
74	78	Optimization of Test Accesses with a Combined BIST and External Test Scheme	claim
75	75	Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts	claim
76	74	Interconnect Energy Dissipation in High-Speed ULSI Circuits	claim
77	60	Transistor Flaring in Deep Submicron-Design Considerations	claim

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