Multiplexer restructuring for FPGA implementation cost reduction

This paper presents a novel synthesis algorithm that reduces the area needed for implementing multiplexers on an FPGA by an average of 18%. This is achieved by reducing the number of Lookup Tables (LUTs) needed to implement multiplexers. The algorithm relies on reimplementing 2:1 multiplexer trees using efficient 4:1 multiplexers. The key to the algorithm’s performance lies in exploiting the observation that most multiplexers occur in busses. New optimizations are employed which pay a small cost in logic that is shared across the bus to achieve a reduction in the logic required for every bit of the bus. Categories and Subject Descriptors B.6.3 [Logic Design]: Design Aids – Automatic Synthesis, Optimization; J.6 [Computer-Aided Engineering]: Computeraided design (CAD). General Terms Algorithms, Performance, Theory. Keywords FPGA, Multiplexers, Restructuring, Recoding, Busses, Logic Optimization, Synthesis.

• Type: Conference
• Year: 2005
• Where: DAC
• Authors: Paul Metzgen, Dominic Nancekievill
• Keywords: Algorithm’s Performance, Computer Architecture, DAC 2005, Logic, Multiplexers