Near-Optimal Precharging in High-Performance Nanoscale CMOS Caches

High-performance caches statically pull up the bitlines in all cache subarrays to optimize cache access latency. Unfortunately, such an architecture results in a significant waste of energy in nanoscale CMOS implementations due to high leakage and bitline discharge in the unaccessed subarrays. Recent research advocates bitline isolation to control precharging of individual subarrays using bitline precharge devices. In this paper, we carefully evaluate the energy and performance trade-offs of bitline isolation, and propose a technique to exploit nearly its full potential to eliminate discharge and reduce overall energy in level-one caches. Cycle-accurate and circuit simulation results of a wide-issue superscalar processor indicate that: (1) in future CMOS technologies (e.g., 70nm and beyond), cache architectures that exploit bitline isolation can eliminate up to 90% of the bitline discharge, (2) ondemand precharging (i.e., decoding the address and subsequently precharging the accessed...

• Type: Conference
• Year: 2003
• Where: MICRO
• Authors: Se-Hyun Yang, Babak Falsafi
• Keywords: Bitline Discharge, Bitline Isolation, Cache Access Latency, Hardware, MICRO 2003