Neural network hardware architecture for pattern recognition in the HESS2 project

In this paper, we consider the problem of implementation of neural network in the context of the level 2 trigger of HESS2 project. We propose a hardware architecture which which takes advantage of high parallelism, pipelining and the intrinsic nature of FPGAs.

• Type: Conference
• Year: 2008
• Where: ESANN
• Authors: Narayanan Ramanan, Sonia Khatchadourian, Jean-Christophe Prévotet, Lounis Kessal
• Keywords: ESANN 2008, Hardware Architecture, Intrinsic Nature, Neural Network, Neural Networks