New decompilation techniques for binary-level co-processor generation

—Existing ASIPs (application-specific instruction-set processors) and compiler-based co-processor synthesis approaches meet the increasing performance requirements of embedded applications while consuming less power than highperformance gigahertz microprocessors. However, existing approaches place restrictions on software languages and compilers. Binary-level co-processor generation has previously been proposed as a complementary approach to reduce impact on tool restrictions, supporting all languages and compilers, at the cost of some decrease in performance. In a binary-level approach, decompilation recovers much of the high-level information, like loops and arrays, needed for effective synthesis, and in many cases yields hardware similar to that of a compiler-based approach. However, previous binary-level approaches have not considered the effects of software compiler optimizations on the resulting hardware. In this paper, we introduce two new decompilation techniques, strength pr...

• Type: Conference
• Year: 2005
• Where: ICCAD
• Authors: Greg Stiff, Frank Vahid
• Keywords: Co-processor Generation, Compiler-based Co-processor Synthesis, Hardware, ICCAD 2005, Software Compiler Optimizations