A New Rounding Algorithm for Variable Latency Division and Square Root Implementations

The aim of this work is to present a method for rounding quadratically converging algorithms that improves their performance. This method is able to reduce significantly the number of cases where the remainder calculation is necessary. It is based on previous methods and incorporates additional bits of the result approximation to be checked. This work includes the result of exhaustive simulations that permit us to measure exactly how many calculations are avoided. Using these simulations, it is concluded that the presented method is able to reduce by half the number of remainder calculations. Using adequate result approximations the remainder calculation is necessary in only 5% of the total cases.

• Type: Conference
• Year: 2008
• Where: DSD
• Authors: D. Piso, Javier D. Bruguera
• Keywords: Additional Bits, DSD 2008, Exhaustive Simulations, Hardware, Remainder Calculation