We introduce an indexing scheme for the vertices of semi-regular meshes, based on interleaving quadtrees rooted on the edges of the base mesh. Using this indexing scheme we develop an out-of-core data structure for semi-regular mesh processing. Our approach targets applications that process vertex data in a coarse-to-fine manner performing several passes through each level of the hierarchy. We consider several measures of layout quality that provide lower bounds on the size of in-core memory buffer required for valid referencing of vertex data during an atomic step of mesh processing. The approach is tested on an in-place implementation of the Loop subdivision scheme for large control meshes.