A Note on Designing Logical Circuits Using SAT

Abstract. We present a systematic procedure for the synthesis and minimisation of digital circuits using propositional satisfiability. We encode the truth table into a canonical sum of at most k different minterms, which is then passed to one randomised search procedure that minimises k. The solution for a minimal k is the satisfiable representation of the resulting circuit. We show how to use an interesting feature of the local search landscape in this minimisation. This approach can be very useful because we can generate exact minimal solutions within reasonably computational resources.

• Type: Conference
• Year: 2003
• Where: ICES
• Authors: Giovani Gomez Estrada
• Keywords: Exact Minimal Solutions, ICES 2003, Local Search Landscape, Systematic Procedure