ICES 2003 - PDF Preprint Papers

ICES 2003 International Conference on Evolvable Systems

Teaser Browsing | Click Here

Title Browsing | Click Here

Wall of Fame | Most Viewed ICES-2003 Paper

click to vote

ICES
2003
Springer

165views Hardware» more ICES 2003»

Speeding up Hardware Evolution: A Coprocessor for Evolutionary Algorithms

14 years 5 months ago

Download www.kip.uni-heidelberg.de

This paper proposes a coprocessor architecture to speed up hardware evolution. It is designed to be implemented in an FPGA with an integrated microprocessor core. The coprocessor r...

Tillmann Schmitz, Steffen G. Hohmann, Karlheinz Me...

claim paper

Read More »

Disclaimer and Copyright Notice

Sciweavers respects the rights of all copyright holders and in this regard, authors are only allowed to share a link to their preprint paper on their own website. Every contribution is associated with a desciptive image. It is the sole responsibility of the authors to ensure that their posted image is not copyright infringing. This service is compliant with IEEE copyright.

Id	Views	Title	Status

1	165	Speeding up Hardware Evolution: A Coprocessor for Evolutionary Algorithms	claim
2	151	Using Genetic Programming and High Level Synthesis to Design Optimized Datapath	claim
3	125	Evolving Reinforcement Learning-Like Abilities for Robots	claim
4	124	Evolving Multiplier Circuits by Training Set and Training Vector Partitioning	claim
5	114	Evolving Fractal Proteins	claim
6	112	Using Negative Correlation to Evolve Fault-Tolerant Circuits	claim
7	111	Spiking Neural Networks for Reconfigurable POEtic Tissue	claim
8	108	A Morphogenetic Evolutionary System: Phylogenesis of the POEtic Circuit	claim
9	105	The Effect of the Bulge Loop upon the Hybridization Process in DNA Computing	claim
10	103	Fault Tolerance via Endocrinologic Based Communication for Multiprocessor Systems	claim
11	101	A Developmental Method for Growing Graphs and Circuits	claim
12	93	A Genetic Representation for Evolutionary Fault Recovery in Virtex FPGAs	claim
13	88	Ontogenetic Development and Fault Tolerance in the POEtic Tissue	claim
14	88	POEtic Tissue: An Integrated Architecture for Bio-inspired Hardware	claim
15	86	A Note on Designing Logical Circuits Using SAT	claim
16	85	Virtual Reconfigurable Circuits for Real-World Applications of Evolvable Hardware	claim
17	79	Using Genetic Programming to Generate Protocol Adaptors for Interprocess Communication	claim

Sciweavers

Explore & Download

Productivity Tools

Document Tools

Image Tools

Sciweavers