A novel improvement technique for high-level test synthesis

Improving testability during the early stages of High-Level Synthesis (HLS) has several benefits, including reduced test hardware overhead, reduced test costs, reduced design iteration, and significant improved fault coverage. In this paper, we present a novel register allocation method, which is based on weighted graph coloring algorithm, targeting testability improvement for digital circuits. The topics covered in this paper include an overview of HLS and testability parameters, our testability model and experimental results. KEYWORDS HLS, register allocation, incompatible variables, conflict graph, weighted graph coloring, simulated annealing.

• Type: Conference
• Year: 2003
• Where: ISCAS
• Authors: Saeed Safari, Hadi Esmaeilzadeh, Amir-Hossein Jahangir
• Keywords: ISCAS 2003, Reduced Test, Testability, Weighted Graph