On the NP-completeness of regular 2-D FPGA routing architectures and a novel solution

Several industrial FPGA routing architectures have been shown to have no efficient routing algorithms (unless P=NP) [3,4]. Here, we further investigate if the intractability of the routing problem on a regular 2-D FPGA routing architecture can be alleviated by adding routing switches. We show that on this routing architecture, even with a substantial increase in switching flexibility, a polynomial time, predictable routing algorithm is still not likely to exist, and there is no constant ratio bound of the detailed over global routing channel densities. We also show that a perfect routing is unachievable on this architecture even with near complete (maximum) switching flexibility. We also discuss a new, greedy routing architecture, that possesses predictable and other desired routing properties, yet requires fewer routing resources than regular architectures. This theoretical result may suggest an alternative approach in routing architecture designs.

• Type: Conference
• Year: 1994
• Where: ICCAD
• Authors: Yu-Liang Wu, Douglas Chang
• Keywords: FPGA Routing Architecture, Hardware, ICCAD 1994, Routing, Routing Architecture