NPCPL: Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs

High throughput and low latency designs are required in modern high performance systems, especially for signal processing applications. Existing logic families cannot provide both of them simultaneously. W e propose a Normal Process Complementary Pass Transistor Logic (NPCPL) which can be used as a univeraal logic t o provide finest grain pipelining without affecting overall latency or increasing the area. It does not require any special process steps and hence, can be Tealised in a normal process technology as against the CPL proposed by Yano et a1 [2] which uses threshold voltage adjustment of selected devices. The design procedure is described for (a)low latency, (b)high throughput and (c)low area requirements. In addition to the various advantages, it is envisioned that NPCPL designs can also be used to build ultra-high speed pipelined system without pipelining latches, viz., wave pipelined digital systems, where the throughput achievable is beyond that permitted by the delay of a...

• Type: Conference
• Year: 1993
• Where: VLSID
• Authors: Debabrata Ghosh, S. K. Nandy, K. Parthasarathy, V. Visvanathan
• Keywords: Low Latency Designs, Normal Process, Throughput, VLSI, VLSID 1993