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VLSID
1993
IEEE
133views VLSI» more  VLSID 1993»
14 years 3 months ago
An Area-Efficient Systolic Architecture for Real-Time VLSI Finite Impulse Response Filters
An area-eficzent systolic architecture for realtime, programmable-coeBcient jinite impulse response (FIR)filters is presented. A technique called pipelined clustering is introduce...
V. Visvanathan, Nibedita Mohanty, S. Ramanathan
VLSID
1993
IEEE
136views VLSI» more  VLSID 1993»
14 years 3 months ago
A Simulation-Based Test Generation Scheme Using Genetic Algorithms
This paper discusses a Genetic Algorithm-based method of generating test vectorsfor detecting faults in combinational circuits. The GA-based approach combines the merits of two te...
M. Srinivas, Lalit M. Patnaik
VLSID
1993
IEEE
114views VLSI» more  VLSID 1993»
14 years 3 months ago
A Methodology for Generating Application Specific Tree Multipliers
Low latency, application, specific multipliers are required for m,any DSP algorithms. Tree multipliers are an obvious answer to this requirement. However, tree architectures have ...
S. Ramanathan, Nibedita Mohanty, V. Visvanathan
VLSID
1993
IEEE
234views VLSI» more  VLSID 1993»
14 years 3 months ago
NPCPL: Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs
High throughput and low latency designs are required in modern high performance systems, especially for signal processing applications. Existing logic families cannot provide both...
Debabrata Ghosh, S. K. Nandy, K. Parthasarathy, V....