An OCM based shared Memory controller for Virtex 4

In this paper, we present a shared instruction and data memory controller for the On-Chip Memory (OCM) bus of the PowerPC embedded in the Virtex-4 chip. The traditional design of the memory controller is implemented on the Processor Local Bus (PLB), which is an undeterministic bus. Our design utilizes the OCM bus which is a dedicated memory bus. As such, the use of the OCM bus allows larger offchip memories (compared to internal BRAMs) to be connected without the overhead of PLB arbitration. Moreover, our design is advantageous because its performance does not depend on the number of connected peripherals on the bus but merely on the delay of the connected DDR memory. Results indicate that, using the shared instruction and data memory controller on the OCM bus, introduces an improvement from 6% to 13% over the PLB based design.

• Type: Conference
• Year: 2007
• Where: FPL
• Authors: Bas Breijer, Filipa Duarte, Stephan Wong
• Keywords: Data Memory Controller, FPL 2007, Hardware, Memory Controller, OCM Bus