OLIVIA: Objectoriented Logicsimulation Implementing the VITAL Standard

In a VHDL-based design flow for applicationspecific integrated circuits, VITAL provides a uniform methodology for developing ASIC libraries for signoff simulation. The VITAL Standard includes specialized routines for describing behavior and timing of ASIC cells and integrates backannotation via Standard Delay Format (SDF). One of the key issues of the VITAL initiative was to accelerate simulation performance at gate level by allowing only a restricted set of VHDL. In this paper, we present an efficient implementation of the VITAL-Standard in our objectoriented, event-driven logic simulation tool OLIVIA. First promising results concerning simulationperformance compared to conventional VHDL-Simulators are given.

• Type: Conference
• Year: 1997
• Where: GLVLSI
• Authors: Josef Fleischmann, Rolf Schlagenhaft, Martin Peller, Norbert Fröhlich
• Keywords: Event-driven Logic Simulation, GLVLSI 1997, Signoff Simulation, VITAL Standard, VLSI