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BIRTHDAY
2012
Springer

Operand Folding Hardware Multipliers

12 years 8 months ago
Operand Folding Hardware Multipliers
This paper describes a new accumulate-and-add multiplication algorithm. The method partitions one of the operands and re-combines the results of computations done with each of the partitions. The resulting design turns-out to be both compact and fast. When the operands’ bit-length m is 1024, the new algorithm requires only 0.194m+56 additions (on average), this is about half the number of additions required by the classical accumulate-and-add multiplication algorithm (m 2 ).
Byungchun Chung, Sandra Marcello, Amir-Pasha Mirba
Added 20 Apr 2012
Updated 20 Apr 2012
Type Journal
Year 2012
Where BIRTHDAY
Authors Byungchun Chung, Sandra Marcello, Amir-Pasha Mirbaha, David Naccache, Karim Sabeg
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