Optimal 2 sub-bank memory architecture for bit plane coder of JPEG2000

—JPEG2000 image compression standard is designed to cater the needs of a large span of applications including numerous consumer products. However, its use is still restricted due to its high computational and memory intensive nature. Bit Plane Coder (BPC) is one of the main resource intensive component of JPEG2000. Due to the unique memory access requirements of BPC, its memory controller and organisation contribute to high percentage of the overall hardware cost. In this paper we present the analysis of the BPC memory requirements and propose an optimal high speed 2 sub-bank based memory architecture. The overall architecture is implemented using Altera FPGA. The experimental results show a savings of 77% in the hardware cost of the memory by keeping the memory requirements to its theoretical lower limit and using a very simple memory controller.

• Type: Conference
• Year: 2005
• Where: ISCAS
• Authors: Amit Kumar Gupta, Saeid Nooshabadi, David S. Taubman
• Keywords: BPC Memory Requirements, ISCAS 2005, Memory Controller, Memory Requirements