Optimal Clock Skew Scheduling Tolerant to Process Variations

1- A methodology is presented in this paper for determining an optimal set of clock path delays for designing high performance VLSI/ULSI-based clock distribution networks. This methodology emphasizes the use of non-zero clock skew to reduce the system-wide minimum clock period. Although choosing (or scheduling) clock skew values has been previously recognized as an optimization technique for reducing the minimum clock period, difficulty in controlling the delays of the clock paths due to process parameter variations has limited its effectiveness. In this paper the minimum clock period is reduced using intentional clock skew by calculating a permissible clock skew range for each local data path while incorporating process dependent delay values of the clock signal paths. Graph-based algorithms are presented for determining the minimum clock period and for selecting a range of processtolerant clock skews for each local data path in the circuit, respectively. These algorithms have been de...

• Type: Conference
• Year: 1996
• Where: DAC
• Authors: José Luis Neves, Eby G. Friedman
• Keywords: Clock, Clock Skew, Computer Architecture, DAC 1996, Minimum Clock Period