Optimal code generation for embedded memory non-homogeneous register architectures

This paper examines the problem of code-generation for expression trees on non-homogeneous register set architectures. It proposes and proves the optimality of an O(n) algorithm for the tasks of instruction selection, register allocation and scheduling on a class of architectures dened as the [1;1] Model. Optimality is guaranteed by sucient conditions derived from the Register Transfer Graph (RTG), a structural representation of the architecture which depends exclusively on the processor Instruction Set Architecture (ISA). Experimental results using the TMS320C25 as the target processor show the ecacy of the approach.

• Type: Conference
• Year: 1995
• Where: ISSS
• Authors: Guido Araujo, Sharad Malik
• Keywords: Hardware, ISSS 1995, Register Allocation, Register Set Architectures, Register Transfer Graph