Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design

—Register allocation, in high-level synthesis and ASIP design, is the process of determining the number of registers to include in the resulting circuit or processor. The goal is to allocate the minimum number of registers such that no scalar variable is spilled to memory. Previously, an optimal polynomial-time algorithm for this problem has been presented for individual procedures represented in Static Single Assignment (SSA) Form. This result is now extended to complete programs (or sub-programs), as long as: (1) each procedure is represented in SSA Form; and (2) at every procedure call, all live variables are split at the call point. With this representation, it is possible to ensure that the interprocedural interference graph (IIG) is chordal, and can therefore be colored optimally in polynomial time. An optimal coloring of the IIG can be achieved by allocating registers for each procedure individually. Previous work has shown that optimal register allocation in SSA Form does not...

• Type: Conference
• Year: 2007
• Where: ICCAD
• Authors: Philip Brisk, Ajay K. Verma, Paolo Ienne
• Keywords: Hardware, ICCAD 2007, Interference Graph, Optimal Polynomial-time Algorithm, Optimal Register Allocation