Scalable interprocedural register allocation for high level synthesis

Abstract— The success of classical high level synthesis has been limited by the complexity of the applications it can handle, typically not large enough to necessitate the departure from the industrial standard, register transfer level design methodology. Recent advances in micro-architecture model enabled the use of a stacked based controller, allowing complex algorithms with multiple procedures to be implemented directly in hardware. Nevertheless, design optimizations across procedure boundaries have not been fully explored. In this paper, we address the problem of interprocedural register allocation in the context of high level synthesis. In contrast to a recently proposed interprocedural register allocation algorithm, which processes an expensive, global, graph representation of the conflict relation of all values to achieve near optimality, we introduce a new method, called color palette propagation (CPP). The key idea behind our method, is to propagate the use of colors, whose...

• Type: Conference
• Year: 2005
• Where: ASPDAC
• Authors: Rami Beidas, Jianwen Zhu
• Keywords: ASPDAC 2005, Interprocedural Register Allocation, Register Allocation Algorithm, Register Transfer Level