Optimization of Arithmetic Datapaths with Finite Word-Length Operands

Abstract: This paper presents an approach to area optimization of arithmetic datapaths that perform polynomial computations over bit-vectors with finite widths. Examples of such designs abound in DSP for audio, video and multimedia computations where the input and output bit-vector sizes are dictated by the desired precision. A bit-vector of size m represents integer values reduced modulo 2m (%2m ). Therefore, finite wordlength bit-vector arithmetic can be modeled as algebra over finite integer rings, where the bit-vector size dictates the ring cardinality. This paper demonstrates how the number-theoretic properties of finite integer rings can be exploited for optimization of bit-vector arithmetic. Along with an analytical model to estimate the implementation cost at RTL, two algorithms are presented to optimize bit-vector arithmetic. Experimental results, conducted within practical CAD settings, demonstrate significant area savings due to our approach.

• Type: Conference
• Year: 2007
• Where: ASPDAC
• Authors: Sivaram Gopalakrishnan, Priyank Kalla, Florian Enescu
• Keywords: ASPDAC 2007, Bit-vector Arithmetic, Bit-vector Size, Finite Integer Rings, Hardware