- An approach for broadband modem FIR filter design optimization is presented. It addresses the minimization of the number of addersubtractors used in the hardware implementation of a FIR filter (Multiple Constant Multiplication problem). The method is based on identification and elimination of n-bit pattern common subexpressions in a set of filter coefficients by means of an exhaustive search. We give an algorithm description of our solution and demonstrate the performance on selected examples. A comparison of the results obtained by other authors is made and finally optimization and synthesis results on a realistic example, a 64-tap root-raised-cosine filter with 10 bit CSD coefficients is given.