Optimization of Test Accesses with a Combined BIST and External Test Scheme

External pins for test are precious hardware resources because this number is strongly restricted. Cores are tested via test access mechanisms (TAMs) such as a test bus architecture. When cores are tested via test buses which have constant bit widths, test stimuli and test responses for a particular core have to be transported over these test buses. The core might require more widths for input and output than test buses, and hence, for some part of the test, the TAMs are idle; this is a wasteful usage of the TAMs. In this paper, an optimization method of test accesses with a combined BIST and external test (CBET) scheme is proposed for eliminating the wasteful usage of test buses. This method can minimize the test time and eliminate the wasteful usage of external pins by considering the trade-off between test time and the number of external pins. Our idea consists of two parts. One is to determine the optimum groups, each of which consists of cores, to simultaneously share mechanisms ...

• Type: Conference
• Year: 2002
• Where: VLSID
• Authors: Makoto Sugihara, Hiroto Yasuura
• Keywords: Computer Architecture, External Test, Test Bus Architecture, Test Buses, VLSID 2002