Optimized on-chip pipelining of memory-intensive computations on the cell BE

Multiprocessors-on-chip, such as the Cell BE processor, regularly suffer from restricted bandwidth to off-chip main memory. We propose to reduce memory bandwidth requirements, and thus increase performance, by expressing our application as a task graph, by running dependent tasks concurrently and by pipelining results directly from task to task where possible, instead of buffering in off-chip memory. To maximize bandwidth savings and balance load simultaneously, we solve a mapping problem of tasks to SPEs on the Cell BE. We present three approaches: an integer linear programming formulation that allows to compute Paretooptimal mappings for smaller task graphs, general heuristics, and a problem specific approximation algorithm. We validate the mappings for dataparallel computations and sorting.

• Type: Journal
• Year: 2008
• Where: SIGARCH
• Authors: Christoph W. Kessler, Jörg Keller
• Keywords: Memory Bandwidth Requirements, Off-chip Main Memory, SIGARCH 2008, Task Graphs