Optimized software synthesis for synchronous dataflow

This paper reviews a set of techniques for compiling dataflow-based, graphical programs for embedded signal processing applications into efficient implementations on programmable digital signal processors. This is a critical problem because programmable digital signal processors have very limited amounts of on-chip memory, and the speed and power penalties for using off-chip memory are often prohibitively high for the types of applications, typically embedded systems, where these processors are used. Moreover, off-chip memory typically needs to be static, increasing the system cost considerably. The compiling techniques described in the paper are developed for the synchronous dataflow model of computation, a model that has found widespread use for specifying and prototyping DSP systems.

• Type: Conference
• Year: 1997
• Where: ASAP
• Authors: Shuvra S. Bhattacharyya, Praveen K. Murthy, Edward A. Lee
• Keywords: ASAP 1997, Digital Signal Processors, Embedded Signal Processing, Hardware, Programmable Digital Signal