Optimizing assignment of threads to SPEs on the cell BE processor

The Cell is a heterogeneous multicore processor that has attracted much attention in the HPC community. The bulk of the computational workload on the Cell processor is carried by eight co-processors called SPEs. The SPEs are connected to each other and to main memory by a high speed bus called the Element Interconnect Bus (EIB), which is capable of 204.8 GB/s. However, access to the main memory is limited by the performance of the Memory Interface Controller (MIC) to 25.6 GB/s. It is, therefore, advantageous for the algorithms to be structured such that SPEs communicate directly between themselves over the EIB, and make less use of memory. We show that the actual bandwidth obtained for inter-SPE communication is strongly influenced by the assignment of threads to SPEs (thread-SPE affinity) in many realistic communication patterns. We identify the bottlenecks to optimal performance and use this information to determine good affinities for common communication patterns. Our solutions...

• Type: Conference
• Year: 2009
• Where: IPPS
• Authors: C. Devi Sudheer, T. Nagaraju, Pallav K. Baruah, Ashok Srinivasan
• Keywords: Cell, Cell Processors, Distributed And Parallel Computing, IPPS 2009, Main Memory