Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space

Parallel prefix adder is the most flexible and widely-used binary adder for ASIC designs. Many high-level synthesis techniques have been developed to find optimal prefix structures for specific applications. However, the gap between these techniques and back-end designs is increasingly large. In this paper, we propose an integer linear programming method to build minimal-power prefix adders within given timing and area constraints. It counts both gate and wire capacitances in the timing and power models, considers static and dynamic power consumptions, and can handle gate sizing and buffer insertion to improve the performance further. The proposed method is also adaptive for non-uniform arrival time and required time on each bit position. Therefore our method produces the optimum prefix adder for realistic constraints.

• Type: Conference
• Year: 2007
• Where: ASPDAC
• Authors: Jianhua Liu, Yi Zhu, Haikun Zhu, Chung-Kuan Cheng, John Lillis
• Keywords: ASPDAC 2007, Hardware, Parallel Prefix Adder, Prefix Adder, Widely-used Binary Adder