In-order pulsed charge recycling in off-chip data buses

This paper presents in-order pulsed charge recycling to reduce energy consumption in an off-chip data bus. The proposed technique performs charge recycling by employing three steps: i) At the beginning of an off-chip data bus transaction, all bus lines which are expected to fall are connected to a common node, ii) next, one at a time and for a fixed period of time, each of the bus lines which are expected to rise are connected to the same common node to allow charge recycling, and finally, iii) regular data bus transaction is resumed by enabling the tri-state buffers to complete the remaining charging (discharging) of the rising (falling) bus lines. Experimental results in Hspice show that the proposed technique achieves 17.4% average energy savings in a 32 bit-wide data bus implemented in a 0.13μm technology with a

• Type: Conference
• Year: 2008
• Where: GLVLSI
• Authors: Kimish Patel, Wonbok Lee, Massoud Pedram
• Keywords: Bus Lines, Data Bus, GLVLSI 2008, Off-chip Data Bus, VLSI