P4: A platform for FPGA implementation of protocol boosters

Protocol Boosters are functional elements, inserted anddeleted fromnetwork protocol stacks on an as-neededbasis. The Protocol Booster design methodology attempts to improve end-to-end networking performance by adapting protocols to network dynamics. We describe a new dynamically recon gurable FPGA based architecture, called the Programmable Protocol Processing Pipeline (P4), which provides a platform for highly- exible hardware implementations of Protocol Boosters. The prototype P4 is designed to interface to an OC3 (155 Mb/s) ATM link and perform selected boosting functions at this line rate. The FPGA devices process the data stream as a pipeline of processing elements. Processing elements are downloaded and activated dynamically, based on policies used by the controller to choose con gurations. As modules become unnecessary they are removed from the pipeline chain.

• Type: Conference
• Year: 1997
• Where: FPL
• Authors: Ilija Hadzic, Jonathan M. Smith
• Keywords: FPL 1997, Fromnetwork Protocol Stacks, Hardware, Protocol Boosters, Protocol Processing Pipeline