Technology mapping can be viewed as the optimization problem of finding a minimum cost cover of the given Boolean network by choosing from given library of logic cells. The core of...
: The paper first proposes requirements for an ideal platform for codesign research. A new board developed at Imperial College, the Riley-2, is shown to meet these requirements. It...
Patrick I. Mackinlay, Peter Y. K. Cheung, Wayne Lu...
Abstract. Pipeline morphing is a simple but e ective technique for recon guring pipelined FPGA designs at run time. By overlapping computation and recon guration, the latency assoc...
Wayne Luk, Nabeel Shirazi, Shaori Guo, Peter Y. K....
Protocol Boosters are functional elements, inserted anddeleted fromnetwork protocol stacks on an as-neededbasis. The Protocol Booster design methodology attempts to improve end-to-...
Controllers for dynamically recon gurable FPGAs that are capable of supporting multiple independent tasks simultaneously need to be able to place designs at run{time when the seque...
In this paper, a temperature-to-frequency transducer suitable for thermal monitoring on FPGAs is presented. The dependence between delay and temperature is used to produce a freque...
We describe the capabilities of and algorithms used in a new FPGA CAD tool, Versatile Place and Route (VPR). In terms of minimizing routing area, VPR outperforms all published FPG...